The process of writing binary computer data to a disk storage device (such as a magnetic or optical disk drive) entails altering a surface characteristic of the disk using an analog carrier signal modulated by the binary data to be recorded. In magnetic disk storage devices, for example, the binary data may modulate the current in the coil of a write head in order to magnetize the surface of the disk in a forward or reverse direction along a concentric data track. For example, a "1" bit may modulate a change of polarity in the current to write a magnetic transition onto the disk, and a "0" bit may modulate no transition (i.e., NRZI encoding). This type of magnetic recording is referred to as "saturation recording" because the magnetization is saturated in one direction or the other as the write head passes over the centerline of the data track during a write operation.
To read the data stored on a particular data track, a read head is aligned over a centerline of the appropriate track in order to transduce the surface alterations into an analog read signal that is ultimately demodulated into an estimated data sequence representing the recorded data. In magnetic disk recording, for example, the read head may comprise a coil which inductively senses the change in the magnetization along the centerline of the track, thereby inducing an analog current in the coil. A magnetic transition induces a pulse in the analog read signal with a polarity corresponding to the direction of the transition. If, for example, a forward-to-reverse transition induces a positive pulse, then a reverse-to-forward transition induces a negative pulse. The pulses in the analog read signal are evaluated (demodulated) in an attempt to estimate the binary data sequence that was originally recorded.
Detecting and demodulating the pulses into the estimated binary sequence can be performed by a simple peak detector in a conventional analog read/write channel or, as in more recent designs, by a discrete time sequence detector in a sampled amplitude read/write channel. Discrete time sequence detectors are preferred over simple analog pulse detectors because they compensate for intersymbol interference (ISI) and are less susceptible to channel noise. Consequently, discrete time sequence detectors increase the capacity and reliability of the storage system.
There are several well known discrete time sequence detection methods including discrete time pulse detection (DPD), partial response (PR) with Viterbi detection, maximum likelihood sequence detection (MLSD), decision-feedback equalization (DFE), enhanced decision-feedback equalization (EDFE), and fixed-delay tree-search with decision-feedback (FDTS/DF). The principles disclosed herein are applicable regardless as to the particular discrete-time sequence detection method employed. The present invention can be used with the above-identified sequence detection methods as well as others not mentioned, and even future techniques. Furthermore, it is contemplated that the present invention is preferably used in a sub-sampled read/write channel, the details for which are described below. However, sub-sampling is not a necessary limitation of the present invention; the general technique described below for writing data to the disk storage medium may be employed in a conventional synchronous sampling read/write channel, or even an analog peak detect read/write channel.
In a conventional peak detection read/write channel, analog circuitry detects peaks in the continuous time analog read signal generated by the read head. The analog read signal is "segmented" into bit cell periods and interpreted during these segments of time. The presence of a peak during the bit cell period is detected as a "1" bit, whereas the absence of a peak is detected as a "0" bit. The most common errors in detection occur when the bit cells are not correctly aligned with the analog pulse data. Timing recovery, then, adjusts the bit cell periods so that the peaks occur in the center of the bit cells on average in order to minimize detection errors. Since timing information is derived only when peaks are detected, the input data stream is normally run-length limited (RLL) to limit the number of consecutive "0" bits.
As the pulses are packed closer together on the data tracks in the effort to increase data density, detection errors can also occur due to intersymbol interference (ISI), a distortion in the read signal caused by closely spaced, overlapping pulses. This interference can cause a peak to shift out of its bit cell, or its magnitude to decrease, resulting in a detection error. This ISI effect is reduced by decreasing the data density or by employing an encoding scheme that ensures a minimum number of "0" bits occur between "1" bits. For example, a (d,k) run length limited (RLL) code constrains to d the minimum number of "0" bits between "1" bits, and to k the maximum number of consecutive "0" bits. A typical (1,7) RLL 2/3 rate code encodes 8 bit data words into 12 bit codewords to satisfy the (1,7) constraint.
Sampled amplitude detection, such as partial response (PR) with Viterbi detection, allows for increased data density by compensating for intersymbol interference and the effect of channel noise. Unlike conventional peak detection systems, sampled amplitude recording detects digital data by interpreting, at discrete time instances, the actual value of the pulse data. To this end, the read/write channel comprises a sampling device for sampling the analog read signal, and a timing recovery circuit for synchronizing the samples to the baud rate (code bit rate). Before sampling the pulses, a variable gain amplifier adjusts the read signal's amplitude to a nominal value, and a low pass analog filter filters the read signal to attenuate channel and aliasing noise. After sampling, a discrete-time equalizer equalizes the sample values according to a desired partial response, and a discrete-time sequence detector, such as a Viterbi detector, interprets the equalized sample values in context to determine a most likely sequence for the digital data (i.e., using maximum likelihood sequence detection (MLSD), or an approximation thereof). MLSD takes into account the effect of ISI and channel noise in the detection algorithm, thereby decreasing the probability of a detection error. This increases the effective signal to noise ratio and, for a given (d,k) constraint, allows for significantly higher data density as compared to conventional analog peak detection read/write channels.
The application of sampled amplitude techniques to digital communication channels is well documented. See Y. Kabal and S. Pasupathy, "Partial Response Signaling", IEEE Trans. Commun. Tech., Vol. COM-23, pp.921-934, September 1975; and Edward A. Lee and David G. Messerschmitt, "Digital Communication", Kluwer Academic Publishers, Boston, 1990; and G. D. Forney, Jr., "The Viterbi Algorithm", Proc. IEEE, Vol. 61, pp. 268-278, March 1973.
Applying sampled amplitude techniques to magnetic storage systems is also well documented. See Roy D. Cideciyan, Francois Dolivo, Walter Hirt, and Wolfgang Schott, "A PRML System for Digital Magnetic Recording", IEEE Journal on Selected Areas in Communications, Vol. 10 No. 1, January 1992, pp.38-56; and Wood et al, "Viterbi Detection of Class IV Partial Response on a Magnetic Recording Channel", IEEE Trans. Commun., Vol. Com-34, No. 5, pp. 454-461, May 1986; and Coker Et al, "Implementation of PRML in a Rigid Disk Drive", IEEE Trans. on Magnetics, Vol. 27, No. 6, November 1991; and Carley et al, "Adaptive Continous-Time Equalization Followed By FDTS/DF Sequence Detection", Digest of The Magnetic Recording Conference, Aug. 15-17, 1994, pp. C3; and Moon et al, "Constrained-Complexity Equalizer Design for Fixed Delay Tree Search with Decision Feedback", IEEE Trans. on Magnetics, Vol. 30, No. 5, September 1994; and Abbott et al, "Timing Recovery For Adaptive Decision Feedback Equalization of The Magnetic Storage Channel", Globecom'90 IEEE Global Telecommunications Conference 1990, San Diego, Calif., November 1990, pp.1794-1799; and Abbott et al, "Performance of Digital Magnetic Recording with Equalization and Offtrack Interference", IEEE Transactions on Magnetics, Vol. 27, No. 1, January 1991; and Cioffi et al, "Adaptive Equalization in Magnetic-Disk Storage Channels", IEEE Communication Magazine, February 1990; and Roger Wood, "Enhanced Decision Feedback Equalization", Intermag'90.
Similar to conventional peak detection systems, sampled amplitude detection requires timing recovery in order to correctly extract the digital sequence. Rather than process the continuous signal to align peaks to the center of bit cell periods as in peak detection systems, sampled amplitude systems synchronize the pulse samples to the baud rate. In conventional sampled amplitude read/write channels, timing recovery synchronizes a sampling clock by minimizing an error between the signal sample values and estimated sample values. A pulse detector or slicer determines the estimated sample values from the read signal samples. Even in the presence of ISI the sample values can be estimated and, together with the signal sample values, used to synchronize the sampling of the analog pulses in a decision-directed feedback system.
A phase-locked-loop (PLL) normally implements the timing recovery decision-directed feedback system. The PLL comprises a phase detector for generating a phase error estimate based on the difference between the estimated samples and the read signal samples. A PLL loop filter filters the phase error, and the filtered phase error operates to synchronize the channel samples to the baud rate.
Conventionally, the phase error adjusts the frequency of a sampling clock which is typically the output of a variable frequency oscillator (VFO). The output of the VFO controls a sampling device, such as an analog-to-digital (A/D) converter, to synchronize the sampling to the baud rate.
Partial response (PR) with Viterbi detection, as mentioned above, is a common method employed in sampled amplitude read/write channels for detecting the recorded digital data from the synchronous sample values. The most common Viterbi type sequence detection methods include: d=0 rate 8/9 PR4, a cost effective implementation requiring only two sliding threshold detectors; and d=1 rate 2/3 EPR4/EEPR4, an implementation which improves the bit error rate (BER) at higher densities but requires a more sophisticated add/compare/select (ASC) type of sequence detector.
The d=1 constraint in the EPR4/EEPR4 read/write channels increases the minimum distance of the corresponding trellis code (and thus decreases the BER), and it reduces the complexity and cost of the sequence detector by taking advantage of symmetry in the trellis model. However, there are drawbacks associated with a d=1 system.
Namely, in d=1 read/write channels, there is a decrease in user data rate due to the decrease in coding efficiency (rate 2/3 for EPR4/EEPR4 as compared to rate 8/9 for PR4). Thus, in order to achieve higher user data rates the channel data rate (code bit rate) must be increased using faster, more complex timing recovery and A/D circuitry (i.e., a higher bandwidth timing recover VCO and A/D converter) which is undesirable because it is not cost effective.
The above referenced patent application entitled "SUB-SAMPLED DISCRETE TIME READ CHANNEL FOR COMPUTER STORAGE SYSTEMS" discloses a read/write channel where the analog read signal is sampled substantially below the baud rate and then interpolated to generate the synchronous sample values. This allows the timing recovery and A/D circuitry to operate at the sub-sampled rate, rather than the baud rate, thereby overcoming the cost and complexity issue described above. However, in that patent application the write circuitry for writing the RLL encoded binary data to the disk is still operated at the baud rate, which is undesirable for the same reasons it is undesirable to sample the read signal at the baud rate (i.e., it increases the cost and complexity of the write circuitry).
There is, therefore, a need for a sampled amplitude read/write channel for use in computer storage systems that can operate at high user data rates and densities without increasing the cost and complexity of the write circuitry, analog-to-digital converter, timing recovery VCO or sequence detector.